A. Technical Field
The present invention relates generally to chip testing, and more particularly, to on-chip analysis and storage of internal integrated circuit signals.
B. Background of the Invention
The importance of integrated circuit (“IC”) technology in various markets and applications is well known. IC technology has progressively evolved resulting in a large number of extremely complex integrated circuits comprising millions of electronic components such as transistors, diodes, resistors, etc. These complex integrated circuits are prone to errors and failure. In order to address these errors, an integrated chip often needs to be tested to address various performance issues of components within the chip.
The complexity of today's IC makes the task of chip-testing more challenging. It is often not possible or quite tedious to analyze a specific IC signal, which may be associated with a particular process being performed within the IC.
Current methods for identifying errors within a chip may require difficult and complex procedures to locate a portion of the IC that has failed. In one example, a chip may be debugged by sending the signals from the chip into a multiplexer so that individual signals may be analyzed. For instance, to examine failure on internal IC signals, the signals may be sent to an external logical multiplexer such as a TEST MUX in which a designer may select the required signal having the problem, amongst various other extra signals coming out of that IC.
The multiplexer can then be used to route the selected signals to an analysis device that may be used by a test engineer. The number of internal signals that are selected may be determined using a hardware-selector that generally goes through a package pad or pin. However, when an attempt to multiplex the internal logical signals to the physical world has to be made, it is necessary to consider signal characteristics such as clocking domains and routing constraints of the desired signals. These characteristics may not be able to be retrieved from the multiplexer or may be inappropriately modified by the multiplexer or hardware selector, which makes the analysis of the signals difficult. Further, greater granularity may be required to analyze different signal groups across different clock domains.
Another approach is to drill into the chip and insert probes for tapping a trace within an IC and extracting data on the trace. One skilled in the art will recognize the inefficiencies of this method and costly equipment required to perform the method. Additionally, this process may also be very time consuming and may take several hours to probe a single IC net.
The approaches mentioned above lack the ability to dynamically select an internal signal within the IC. Furthermore, these approaches fail to address signal routing and timing complications that may be relevant in testing the IC. Additionally, these methods lack the ability to multiplex out signals from different clock domains; making it less flexible across various signal groups.
Therefore, there is a need for an apparatus and a method that address the above-described limitations.